1. Field of Invention
The present invention relates to a high performance serial bus, and more particularly, to a method of generating multiple self-ID packets over a high performance serial bus to map a node topology in a network.
2. Description of the Invention
In general, most of the digital electronic systems today typically utilize a common interconnection to share information between different components of the system. One type of the well-known system protocols that may be used in this type of interconnection system is set forth in the IEEE High Performance Serial Bus 1394 standard, which is incorporated herein by reference. Basically, the 1394 standard defines, as shown in FIG. 1, a three-layered system including a physical layer, a link layer, and a transaction layer. The function of the physical layer 10 is to specify the signals required in the 1394 bus, the link layer 12 provides the means to format the data from the physical layer into recognizable data packets, the transaction layer 14 forwards the data received from the link layer to an application, and the serial bus management block 16 provides the basic control functions and manages the bus resources.
Referring to FIG. 2, the function of these different layers is implemented in the dedicated, integrated circuits 20, each having one or more I/O circuits. The physical layer connected to the 1394 bus 22 can be implemented in a physical layer chip 24, or xe2x80x9cPHY chip.xe2x80x9d The link layer can be implemented in a link chip 26. As set forth under the IEEE 1394 standard, the PHY chip serves to transmit and receive I/O signals and performs system initialization, bus arbitration, and the associated handshaking to transmit data over the bus. Accordingly, the 1394 standard defines an electrical and physical interface, including various signaling and data transmission protocols, for interconnection of the 1394 devices (or nodes) via cables or an electrical backplane in point-to-point links. The 1394 standard allocates up to 63 nodes to be connected to a single 1394 bus, and also multiple buses may be interconnected via 1394 bridge nodes. There are three possible speeds at which data packets can be transmitted between nodes on the bus. They are 100, 200, and 400 megabits per second. The speed at which a data packet can be transmitted depends on the bus topology and the data transmission speeds supported by various nodes on the bus. Here, a topological map of the bus network is required in order to determine the optimum packet transmission speed.
In addition, reconfiguration of the serial bus is required whenever a node is added to or removed from the 1394 bus. The reconfiguration (or bus reset) is necessary to ensure that all nodes of the serial bus are notified of the newly connected or disconnected node. To this end, each node has a unique bus address. Three stages of the configuration process include bus initialization, tree identification (tree-ID), and self identification (self-ID) phases. During the bus initialization stage, a bus reset signal forces all nodes to clear all topology information of the network. At this time, the only information known to a node is whether it is a branch (more than one directly connected neighbor), a leaf (only a single neighbor), or isolated (unconnected). Thereafter, the tree-ID process translates the network topology into a tree, where one node is designated a root and the remaining connections are labeled as a xe2x80x9cparentxe2x80x9d (a node that is closer to the root node) and xe2x80x9cchildxe2x80x9d (a node that is further from the root node). Finally, each node is assigned to a unique self-ID for identifying purposes to any management entity attached to the bus so that a system topology map can be built. The self-ID process uses a deterministic selection process where the root node passes control of the media to the node attached to its lowest-numbered connected port and waits for that node to signal that it and all of its children have transmitted their self-ID packets. The root then passes control to its next highest port and waits for that node to finish. When the nodes attached to all the root""s ports have finished, the root itself transmits its self-ID packet. The child nodes use the same process in a recursive manner.
During the self-ID phase, a unique physical ID is assigned to each node, and each node on the bus is given an opportunity to transmit one to four short packets onto the 1394 cable which includes the physical ID, port connection status, and some additional management information. Here, the physical ID is simply the count of the number of times a node passes through the state of receiving self-ID information before having its own opportunity to do so. Accordingly, as all information necessary to determine the bus topology is contained in the self-ID packet, power management can be performed and bus topological information can be obtained.
The conventional physical layer implemented by a PHY chip as set forth under the IEEE 1394 standard has some drawbacks in supporting the configuration management of a 1394 high performance. The 1393 PHY chip participates in the self-ID process by broadcasting a set of self-ID packets (one or four packets, depending on the number of its ports) that associates with the corresponding single node. However, the 1394 PHY chip can represent only one node. Thus, if a need arises to send a self-ID packet with some modification of information thereto, additional 1394 PHY chips are required as the bit information in the self-ID packet is unchangeable.
Therefore, what is desired are some efficient methods and apparatuses for providing I/O circuits for use with a PHY circuit, wherein the I/O circuits are capable of generating multiple self-IDs corresponding to multiple nodes utilizing a single 1394 PHY chip.
It is, therefore, an objective of the present invention to provide a configuration management for a high performance serial bus by generating multiple self-ID packets on a 1394 bus using a standard PHY chip.
It is another objective of the present invention to efficiently build and represent a topological map of the bus network including actual nodes connected to the bus as well as virtual nodes that are not actually present in the network.